simplemaster.h from GreenSocs at Krugle

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#define MEMSIZE 10000
#define VERBOSE

#include <systemc.h>

#include "gstlm/gstlm/tlm.h"
#include "gstlm/protocol/generic.h"
#include "gstlm/userAPI/basicPorts.h"

using namespace tlm;



/**
 * A simple bus master that plays with the protocol.
 */
class simplemaster : public sc_module
{
public:
  GenericMasterPort init_port;

private:
  typedef GenericMasterPort::accessHandle transactionHandle;
  typedef GenericMasterPort::phaseHandle phaseHandle;

  unsigned char mem[MEMSIZE];

  
  sc_event ft;
  int pending;
  unsigned long long tadd;
  
  void test_wr();
  void test_rd();

public:

  //Constructor
  SC_HAS_PROCESS(simplemaster);

  /**
   * Simplemaster constructor.
   * @param name_ The module name.
   * @param targetAddress The target memory address. 
   * @param data Initial memory content.
   * @param rNw This parameter controls whether this master does write or read transactions.
   */
  simplemaster(sc_module_name name_, unsigned long long targetAddress, const char* data = NULL, bool rNw = false) : 
    sc_module(name_),init_port("iport") {
    tadd=targetAddress;

    // init memory
    bzero((char*)mem, MEMSIZE);
    if (data != NULL)
      strcpy((char *)(mem),data);

    cout<<"Hello my name is "<<name()<<" and my port's id is "<<init_port.get_master_port_number()<<endl<<flush;
    pending=0;

    if(rNw) {     
      GSTRACE("running in READ mode.");
      SC_THREAD(test_rd);
      sensitive(init_port.default_event()); // listen to bus phases at BA
    }
    else{
      GSTRACE("running in WRITE mode.");
      SC_THREAD(test_wr);
      sensitive(init_port.default_event()); // listen to bus phases at BA
    }
  }
};

/**
 * Test read transaction using the PLB protocol.
 */
void simplemaster::test_rd(){
    transactionHandle t1 = init_port.create_transaction();
    GenericMasterPort::accessHandle tah;
    GenericMasterPort::phaseHandle phase;

    t1->set_mCmd(Generic_MCMD_RD);
    t1->set_mAddr(tadd);
    t1->set_mBurstLength(strlen((char *)mem)+1);
    t1->set_mData(MasterDataType(&mem[0],strlen((char *)mem)+1));

    init_port.Request(t1);
    wait();

    tah=init_port.get_transactionHandle();
    phase=init_port.get_phase();

    if(phase.state==GenericPhase::RequestAccepted)
      GSTRACE("got requestAccepted.");
    else
      SC_REPORT_ERROR(name(), "wrong phase!");
    wait();

    tah=init_port.get_transactionHandle();
    phase=init_port.get_phase();
    if(phase.state==GenericPhase::ResponseValid){
      GSTRACE("slave sent data!");
    }
    else
      SC_REPORT_ERROR(sc_core::SC_ID_INTERNAL_ERROR_, "wrong protocol phase!");

    MasterDataType my_data;
    my_data.set(tah->get_sData());

    cout<<name()<<" @ "<<sc_time_stamp()<<": got data [";
    for (unsigned int i=0; i<tah->get_mBurstLength(); i++)
      cout<<my_data[i]<<flush;
    cout<<"]"<<endl<<flush;

    // send response ack
    init_port.AckResponse(tah, phase);
}


/**
 * Test write transaction using the PLB protocol.
 */
void simplemaster::test_wr(){
    transactionHandle t1 = init_port.create_transaction();
    GenericMasterPort::accessHandle tah;
    GenericMasterPort::phaseHandle phase;

    t1->set_mCmd(Generic_MCMD_WR);
    t1->set_mAddr(tadd);
    t1->set_mData(MasterDataType(&mem[0],strlen((char *)mem)+1));
    t1->set_mBurstLength(strlen((char *)mem)+1);

    // send write request
    init_port.Request(t1);
   
    wait(); // wait for ACK

    tah=init_port.get_transactionHandle();
    phase=init_port.get_phase();

    if(phase.state==GenericPhase::RequestAccepted)
      GSTRACE("master got reply!");
    else
      SC_REPORT_ERROR(name(),"wrong phase");

    // send data to the slave
    init_port.SendData(t1, phase);

    wait(); // wait for ACK

    tah=init_port.get_transactionHandle();
    phase=init_port.get_phase();
    if(phase.state==GenericPhase::DataAccepted)
      GSTRACE("slave accepted the data!");
    else
      SC_REPORT_ERROR(sc_core::SC_ID_INTERNAL_ERROR_, "wrong phase");

}
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