PLBBusProtocol.h from GreenSocs at Krugle

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/*
Copyright (c) 2006 : Technical University of Braunschweig, Germany

All rights reserved.

Authors: Robert Guenzel, Wolfgang Klingauf, TU Braunschweig, E.I.S.

Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:

Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.  Redistributions
in binary form must reproduce the above copyright notice, this list of
conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.  Neither the name of
the Technical University of Braunschweig, Germany nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/

#ifndef __busProtocol_h__
#define __busProtocol_h__

#include <systemc.h>
#include "gstlm/router/genericProtocol_if.h"
#include "gstlm/router/genericRouter_if.h"
#include "gstlm/router/genericScheduler_if.h"

#include "gstlm/gstlm/tlm.h"
#include "gstlm/protocol/PLB.h"
#include <map>

/**
 *
 */

using namespace tlm;
using namespace PLB;

class PLBBusProtocol: public GenericProtocol_if<PLBTransaction, GenericPhase>, public sc_module
{
  typedef tlm::unevenpair<PLBTransaction_P,GenericPhase> pair_type;

  typedef sc_export<payload_event_queue_if<tlm::unevenpair<boost::shared_ptr<PLBTransaction>,tlm::GenericPhase > > > * sourcePort;

  typedef sc_export<payload_event_queue_if<tlm::unevenpair<boost::shared_ptr<PLBTransaction>,tlm::GenericPhase > > > * destinationPort;

public:

  sc_port<GenericRouter_if<initiator_multi_port<PLBTransaction,PLBRouterAccess,GenericPhase>, 
                           target_multi_port<PLBTransaction,PLBRouterAccess,GenericPhase> > > router;
  sc_port<GenericScheduler_if<PLBTransaction, GenericPhase> > scheduler;

  SC_HAS_PROCESS(PLBBusProtocol);
  PLBBusProtocol(sc_module_name name, double time, sc_time_unit base);

  virtual bool registerMasterAccess(pair_type& transaction);
  virtual bool processMasterAccess();
  virtual bool registerSlaveAccess(pair_type& transaction);
  virtual bool processSlaveAccess();

  virtual void assignProcessMasterAccessSensitivity(sc_process_b* pMethod);
  virtual void assignProcessSlaveAccessSensitivity(sc_process_b* pMethod);

  virtual void end_of_elaboration();

private:
  sc_event_queue startMasterAccessProcessing;
  sc_event startSlaveAccessProcessing;
  //PLBAddressMap<unsigned long long int> m_addressMap;
  std::map<unsigned int, unsigned int> m_masterMap;

  //well... what do we need for PLB?
  //TRANS_STORAGE(m_queue); //a request queue, I guess
  sc_time m_clkPeriod; //a clock period of course!
  sc_time m_halfClkPeriod; //half of the clock period, to avoid run time division
  pair_type m_waitingSecondaryWriteData; //a place where we can "park" secondary write data
  bool m_secoWriteDataValid; //a bool indicating that there is valid write data waiting
  pair_type m_activeSecoRdReq; //a link to the active secondary request, to signal promotion to primary
  pair_type m_activeSecoWrReq; //a link to the active secondary request, to signal promotion to primary
  pair_type m_activePrimReq; 
  unsigned int m_activePrimWrMaster; //the ID of the primary writing master
  unsigned int m_activeSecoWrMaster; //the ID of the secondary writing master
  unsigned int m_activePrimRdMaster; //the ID of the primary writing master
  unsigned int m_activeSecoRdMaster; //the ID of the secondary writing master
  sc_time m_wrCompTime; //the time the last write was completed
  sc_time m_rdCompTime; //the time the last read  was completed
  bool m_secoRdAck; //a bool indicating whether the seq request was acked yet or not
  bool m_secoWrAck; //a bool indicating whether the seq request was acked yet or not
  unsigned int m_activePrimWrSlavePortRank; //the port rank of the recent targeted (write) slave (saves decoding time)
  unsigned int m_activePrimRdSlavePortRank; //the port rank of the recent targeted (read)  slave (saves decoding time)
  unsigned int m_activeSecoWrSlavePortRank; //the port rank of the recent targeted (write) slave (saves decoding time)
  unsigned int m_activeSecoRdSlavePortRank; //the port rank of the recent targeted (read)  slave (saves decoding time)
  sc_event m_TOEvent; //an event for timeouts
  bool m_addressStageBusy; //indicator that address stage is busy
  sc_time m_addressAckTime; //time of last aAck
  sc_event m_promotionEvent; //event that gets triggered, when a secondary request gets promoted to primary
  sc_time m_rdReqDeliverTime; //the time a request arrives at the slave
  sc_time m_wrReqDeliverTime; //the time a request arrives at the slave
  bool m_promoteWr; //a bool indicating whether there's a seco write to promote
  bool m_promoteRd; //a bool indicating whether there's a seco read  to promote
  volatile bool m_timedOut; //a semaphore

  void promote(bool rNw, int delay); //helper function

  void delayedPromotion(); //sc_method

};

#include "PLBBusProtocol.tpp"

#endif
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