Show simplebusAPI.h syntax highlighted
/*
Copyright (c) 2006 : Technical University of Braunschweig, Germany
All rights reserved.
Contact: Wolfgang Klingauf
TU Braunschweig, E.I.S.
<klingauf@eis.cs.tu-bs.de>
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer. Redistributions
in binary form must reproduce the above copyright notice, this list of
conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution. Neither the name of
the Technical University of Braunschweig, Germany nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __simplebusAPI_h__
#define __simplebusAPI_h__
/**
* \file simplebusAPI.h
* The simplebusAPI provides two blocking bus access methods:
* read, write.
* It is a simple example for a GreenBus User-API.
* Furthermore, it shows how slaves that _themselfes_ implement
* a TLM API (rather than waiting for a bus event)
* can be connected to GreenBus.
*/
#include "systemc.h"
#include "utils/gs_datatypes.h"
#include "utils/gs_trace.h"
#include "protocol/generic.h"
namespace tlm {
///////////////////////////////////////////////////////////////////////////////
/// The simplebus interface
///////////////////////////////////////////////////////////////////////////////
/**
* This is a blocking interface for TLM communication.
* The interface provides blocking methods for both
* single-beat, and burst read and write transactions.
*/
class simplebus_if : virtual public sc_interface
{
public:
/// Read data from a slave
/**
* Read data from a SimpleBus slave. The transaction
* may be of arbitrary length.
* The implementation of this method has to be blocking
* and must not return until the data has been
* completely received from the slave.
* @param data Data array into which the data will be copied
* that is received from the slave.
* @param addr Target address of the slave.
* @param length Burst length
* @return true on success,
* false if no slave is present at the specified target address.
*/
virtual bool read(std::vector<gs_uint8> &data,
const gs_uint32 addr,
const gs_uint32 length) =0;
/// Write data to a slave
/**
* Write data to a SimpleBus slave. The transaction
* may be of arbitrary length.
* The implementation of this method has to be blocking
* and must not return until the data has been
* completely received by the slave.
* @param data Data array to send to the slave.
* @param addr Target address of the slave.
* @param length Burstlength
* @return true on susccess,
* false if no slave is present at the specified target address.
*/
virtual bool write(const std::vector<gs_uint8> &data,
const gs_uint32 addr,
const gs_uint32 length) =0;
};
///////////////////////////////////////////////////////////////////////////////
/// The simplebus master port
///////////////////////////////////////////////////////////////////////////////
/**
* This is the master port. It provides a read and a write method.
* Both methods are blocking.
* Use this port in a SimpleBus master to get access to a SimpleBus slave.
*/
class simplebusMasterPort
: public GenericMasterPort
{
public:
typedef GenericMasterPort PORT;
typedef PORT::accessHandle accessHandle;
typedef PORT::phase phase;
protected:
sc_event readDoneEvent;
public:
/// simulation mode: 0=BA (default), 1=PV (use b_transact)
gs_param<gs_uint32> simulation_mode;
SC_HAS_PROCESS(simplebusMasterPort);
/**
* Create a simplebusMasterPort. Use configuration framework
* to set parameters target_addr and simulation_mode.
*/
simplebusMasterPort(sc_module_name _name)
: PORT(_name)
{
#ifdef DUST_ENABLE
DUST_MASTER_PORT("SimpleBusMasterPort", "SimpleBus");
#endif
SC_METHOD(react);
sensitive << PORT::default_event();
dont_initialize();
GS_PARAM(simulation_mode, gs_uint32, 0); // default mode is BA
}
/**
* The simplebus_if read method.
*/
bool read(std::vector<gs_uint8> &data, const gs_uint32 addr, const gs_uint32 length) {
accessHandle ah = PORT::create_transaction();
MData mdata(data);
ah->setMAddr(addr);
ah->setMBurstLength(length);
ah->setMCmd(Generic_MCMD_RD);
ah->setMData(data); // slave copies its data into the master's vector
if (simulation_mode == 0) { // BA
bool success=false;
while (!success) {
GS_TRACE(name(), "read() sending RequestValid with MAddr=0x%x, MBurstLength=%d", addr, length);
PORT::Request.block(ah, SC_ZERO_TIME, MODE_BA);
phase ph = PORT::get_phase();
if (ph.isRequestAccepted())
success=true;
else
GS_TRACE(name(), "read() got unknown answer to RequestValid: phase=%s. Ignoring.", ph.toString().c_str());
}
sc_core::wait(readDoneEvent); // wait for slave response
}
else { // PV
GS_TRACE(name(), "read() doing PV read transaction with MAddr=0x%x, MBurstLength=%d", addr, length);
PORT::Transact(ah);
}
if (ah->getSError() != GenericError::Generic_Error_NoError) {
SC_REPORT_WARNING(name(), "read() transaction was terminated by slave with an error.");
return false;
}
return true;
}
/**
* The simplebus_if write method.
*/
bool write(const std::vector<gs_uint8> &data, const gs_uint32 addr, const gs_uint32 length) {
accessHandle ah = PORT::create_transaction();
MData mdata(data);
ah->setMAddr(addr);
ah->setMBurstLength(length);
ah->setMCmd(Generic_MCMD_WR);
ah->setMData(mdata);
if (simulation_mode == 0) { // BA
GS_TRACE(name(), "write() sending RequestValid with MAddr=0x%x, MBurstLength=%d", addr, length);
bool success=false;
phase ph;
while (!success) {
PORT::Request.block(ah, SC_ZERO_TIME, MODE_BA);
ph = PORT::get_phase();
if (ph.isRequestAccepted())
success=true;
else
GS_TRACE(name(), "write() got unknown answer to RequestValid: phase=%s. Ignoring", ph.toString().c_str());
}
PORT::SendData.block(ah, ph, SC_ZERO_TIME, MODE_BA);
}
else { // PV
GS_TRACE(name(), "write() doing PV write transaction with MAddr=0x%x, MBurstLength=%d", addr, length);
PORT::Transact(ah);
}
if (ah->getSError() != GenericError::Generic_Error_NoError) {
SC_REPORT_WARNING(name(), "read() transaction was terminated by slave with an error.");
return false;
}
return true;
}
/**
* Play the generic protocol with GreenBus.
*/
void react() {
accessHandle ah = PORT::get_transaction();
phase ph = PORT::get_phase();
if (ph.isResponseValid()) {
PORT::AckResponse(ah, ph, SC_ZERO_TIME, ph.getSimulationMode());
GS_TRACE(name(), "react() got ResponseValid. Sending AckResponse.");
readDoneEvent.notify();
}
else if (ph.isRequestAccepted() || ph.isDataAccepted()) {}
else
{
GS_TRACE(name(), "react() got triggered by unknown phase=%s. Ignoring.", ph.toString().c_str());
}
}
};
///////////////////////////////////////////////////////////////////////////////
/// The simplebus slave port
///////////////////////////////////////////////////////////////////////////////
/**
* This is the slave port. Bind this port with a GreenBus router, and bind a
* SimpleBus slave to this port.
*/
class simplebusSlavePort
: public GenericSlavePort,
public tlm_b_if<TRANSACTION_P>
{
public:
typedef GenericSlavePort PORT;
typedef PORT::accessHandle accessHandle;
typedef PORT::phase phase;
/// slave module socket
sc_port<simplebus_if> slave_port;
SC_HAS_PROCESS(simplebusSlavePort);
/**
* Create a SimpleBus slave port. Use configuration framework
* to set address range (base_addr, high_addr) of the slave.
*/
simplebusSlavePort(sc_module_name _name)
: PORT(_name)
{
#ifdef DUST_ENABLE
DUST_SLAVE_PORT("SimpleBusSlavePort", "SimpleBus");
#endif
PORT::bind_b_if(*this);
SC_THREAD(react);
//sensitive << PORT::default_event();
//dont_initialize();
}
/**
* The tlm_b_if PV transaction method
*/
virtual void b_transact(transactionHandle th) {
//sc_assert(th->getMBurstLength()>0);
if (th->getMCmd() == Generic_MCMD_WR) {
if (slave_port->write(th->getMData().getData(),
static_cast<gs_uint32>(th->getMAddr())-static_cast<gs_uint32>(base_addr.value),
static_cast<gs_uint32>(th->getMBurstLength()))) {
th->setSBurstLength(th->getMBurstLength());
}
else { // error
th->setSError(GenericError::Generic_Error_AccessDenied);
SC_REPORT_WARNING(name(), "b_transact() slave_port->write() returned false. Setting SError=Generic_Error_AccessDenied.");
}
}
else if (th->getMCmd() == Generic_MCMD_RD) {
if (slave_port->read(th->getSData().getData(),
static_cast<gs_uint32>(th->getMAddr())-static_cast<gs_uint32>(base_addr.value),
static_cast<gs_uint32>(th->getMBurstLength()))) {
th->setSBurstLength(th->getMBurstLength());
}
else { // error
th->setSError(GenericError::Generic_Error_AccessDenied);
SC_REPORT_WARNING(name(), "b_transact() slave_port->read() returned false. Setting SError=Generic_Error_AccessDenied.");
}
}
else {
SC_REPORT_WARNING(name(), "b_transact() got unknown MCmd. Ignoring. Setting SError=Generic_Error_AccessDenied.");
th->setSError(GenericError::Generic_Error_AccessDenied);
}
}
/**
* Play the generic protocol with GreenBus.
*/
void react() {
MCmd cmd = Generic_MCMD_IDLE;
while (1) {
sc_core::wait(PORT::default_event());
accessHandle ah = PORT::get_transaction();
phase ph = PORT::get_phase();
switch(ph.state) {
case GenericPhase::RequestValid: // master sends request
{
cmd = ah->getMCmd();
if (cmd != Generic_MCMD_WR && cmd != Generic_MCMD_RD) {
SC_REPORT_WARNING(name(), "react() got unknown MCmd in RequestValid phase. Ignoring. Sending Request Error with SError=Generic_Error_AccessDenied.");
ah->setSError(GenericError::Generic_Error_AccessDenied);
PORT::ErrorRequest(ah, ph, SC_ZERO_TIME, ph.getSimulationMode());
}
else {
PORT::AckRequest(ah, ph, SC_ZERO_TIME, ph.getSimulationMode());
if (cmd == Generic_MCMD_RD) { // read request
GS_TRACE(name(), "react() got RequestValid with MCmd=Generic_MCMD_RD, MBurstLength=%d. Calling slave_port->read().", (gs_uint32)ah->getMBurstLength());
if (slave_port->read(ah->getSData().getData(),
static_cast<gs_uint32>(ah->getMAddr())-static_cast<gs_uint32>(base_addr.value),
static_cast<gs_uint32>(ah->getMBurstLength()))) {
ah->setSBurstLength(ah->getMBurstLength());
GS_TRACE(name(), "react() slave_port->read() returned. Sending ResponseValid.");
if (ph.getSimulationMode()==MODE_CT) { // play the CT protocol
SC_REPORT_ERROR(name(), "CT mode not implemented.");
}
else {
PORT::Response(ah, ph, SC_ZERO_TIME, ph.getSimulationMode());
}
}
else {
SC_REPORT_WARNING(name(), "react() slave_port->read() returned false. Sending ResponseValid with SError=Generic_Error_AccessDenied.");
ah->setSError(GenericError::Generic_Error_AccessDenied);
PORT::Response(ah, ph, SC_ZERO_TIME, ph.getSimulationMode());
}
}
else { // write command
GS_TRACE(name(), "react() got RequestValid with MCmd=Generic_MCMD_WR, MBurstLength=%d. Sending AckRequest.", (gs_uint32)ah->getMBurstLength());
}
}
}
break;
case GenericPhase::DataValid: // master sends data
{
sc_assert(cmd==Generic_MCMD_WR);
GS_TRACE(name(), "react() got DataValid with MBurstLength=%d. Calling slave_port->write().", (gs_uint32)ah->getMBurstLength());
if (slave_port->write(ah->getMData().getData(),
static_cast<gs_uint32>(ah->getMAddr())-static_cast<gs_uint32>(base_addr.value),
static_cast<gs_uint32>(ah->getMBurstLength()))) {
ah->setSBurstLength(ah->getMBurstLength());
GS_TRACE(name(), "react() slave_port->write() returned. Sending AckData. Write transaction finished.");
if (ph.getSimulationMode()==MODE_CT) { // play the CT protocol
SC_REPORT_ERROR(name(), "CT mode not implemented.");
}
else {
PORT::AckData(ah, ph, SC_ZERO_TIME, ph.getSimulationMode());
}
}
else {
SC_REPORT_WARNING(name(), "react() slave_port->write() returned false. Sending DataError with SError=Generic_Error_AccessDenied.");
ah->setSError(GenericError::Generic_Error_AccessDenied);
PORT::ErrorData(ah, ph, SC_ZERO_TIME, ph.getSimulationMode());
}
cmd = Generic_MCMD_IDLE;
}
break;
case GenericPhase::ResponseAccepted: // master acks response
{
GS_TRACE(name(), "react() got ResponseAccepted. Read transaction finished.");
cmd = Generic_MCMD_IDLE;
}
break;
default:
{
GS_TRACE(name(), "react() got unknown phase [%s]", ph.toString().c_str());
SC_REPORT_WARNING(name(), "react() got triggered with unexpected phase. Ignoring.");
}
}
}
}
};
class simplebusMasterPortForward: public basic_port_forwarder<simplebusMasterPort, simplebusSlavePort, GenericTransaction, GenericPhase> {
public:
simplebusMasterPortForward(sc_module_name name): basic_port_forwarder<simplebusMasterPort, simplebusSlavePort, GenericTransaction, GenericPhase>(name){}
};
class simplebusSlavePortForward: public basic_port_forwarder<simplebusSlavePort, simplebusMasterPort, GenericTransaction, GenericPhase> {
public:
simplebusSlavePortForward(sc_module_name name): basic_port_forwarder<simplebusSlavePort, simplebusMasterPort, GenericTransaction, GenericPhase>(name){}
};
} // namspace tlm
#endif // __simplebusAPI_h__
See more files for this project here